A very important device of the type characterized generally above is the self-aligned gate MESFET. Self-aligned gate technology is adapted to enhance high frequency performance by using the gate as a mask to create the FET source and drain, thereby to get almost perfect alignment between those elements. In addition, as such circuits become miniaturized for purposes such as MMIC's (monolithic microwave integrated circuits), it is important to increase circuit density which requires precise alignment between multiple layers as they are deposited one upon the other during the semiconductor fabrication process.
The prior art has employed high melting point metallic gates, such as metal silicides, for example tungsten silicide, because the high melting point property of those gates can withstand the relatively high annealing temperatures applied during formation of the source and drain regions after deposition of the gate. One prior art technique using a metal silicide gate is described in connection with FIGS. 2(a)-2(d). Those figures show cross-sectional structures illustrating the process steps of one prior art method for producing a self-aligned gate MESFET device.
FIG. 2(a) shows an early stage of device production in which an active layer 2 is produced in a semi-insulative GaAs substrate 1 by ion implantation. A high melting point metal silicide layer 3, such as tungsten silicide, is plated by evaporation or sputtering over the entire exposed surface of the active layer 2. A gate pattern is formed on the layer 3 by means of a photoresist film 6 which is exposed and processed to protect the gate region while leaving the remaining area of the layer 3 exposed to an etching process.
Advancing to FIG. 2(b), it is seen that a gate electrode is produced by reactive ion etching of the high melting point metal silicide layer 3 using the photoresist film 6 as a mask. Following the etching step, the high melting point metal silicide gate can then serve as a mask for formation of the source and drain regions in the semiconductor substrate. As is known in the art, after removing residuals by an acid wash, ion implantation into substrate 1 is carried out using the metal silicide gate as a mask to form highly doped regions 8 (FIG. 2(c)) which become source or drain regions. Having implanted impurities into the regions 8, the device is then annealed at an elevated temperature, such as 800.degree. C. to allow the implanted atoms to move into appropriate locations in the lattice sites. Then source and drain electrodes 7 are deposited using conventional vapor plating lift-off techniques to obtain a completed MESFET device as illustrated in FIG. 2(d).
It is because of the high temperature annealing that the high temperature properties of the gate 3 are important. More particularly, it is necessary having used the gate 3 to align the source and drain, to maintain the gate in its appropriate location to retain the desired alignment, thereby to assure best high frequency performance. Although the high melting point metal silicide gate of this prior art technique is produced by the self-aligning method as described above, the resistance of the gate electrode is relatively high. As a result, the field effect transistor thus produced has a noise figure which deteriorates at high frequencies, limiting its use in high frequency applications.
It is known that one of the solutions to the high frequency noise problem is to deposit a low resistance metal on the high melting point metal silicide gate. Adopting that approach reduces the resistance in the gate circuit, and thus improves high frequency performance. While it is possible to crudely deposit a low resistance metal such as aluminum or gold over and in the general vicinity of the high melting point silicide gate, in order to maintain the benefits of miniaturization as they relate to high packing density as well as high frequency operation, attempts have been made to produce a low resistance gate on the high melting point silicide gate in a self-aligning manner.
One such technique is illustrated in FIGS. 3(a)-3(h). FIG. 3(a) illustrates the initial stages of a process in which a GaAs substrate 1 has n-type dopant material ion implanted in an active layer 2, following which a high melting point metal silicide film 3 is deposited on the substrate surface. An insulating layer 11, such as SiO.sub.2, is then deposited on the high melting point metal silicide film 3 by sputtering, evaporation or CVD techniques. A photoresist film 6 is then deposited over the double layer 3, 11 to form the pattern for a gate region.
Progressing to FIG. 3(b), it is seen that reactive ion etching is used to etch the layers 3, 11 using the photoresist 6 as a mask thereby to produce a structure including high melting point metal silicide layer 3 and insulating layer 11 on the substrate 1. Films 3 and 11 may be etched simultaneously under the same conditions, or a separate etching process may be carried out for each of the two films. The nature of the etchant gas, the power supplied and the processing time are process conditions that determine the etching conditions for the respective layers. Following reactive ion etching, acid is used to remove residual materials, including the photoresist film 6 or plasma polymerization.
As in the prior embodiment, after forming the gate structure, the gate is used as a mask for a subsequent ion implantation and annealing operations which form highly doped regions 8 to serve as the source and drain (see FIG. 3(c)). The high temperature characteristics of the regions 3, 11 are important in surviving the annealing operation to provide a self-aligned gate.
Following ion implantation and annealing, which typically takes place at about 800.degree. C., source and drain electrodes 7 (FIG. 3(d)) are formed by evaporation and lift-off. Thereafter, as shown in FIG. 3(e), a photoresist film 9 is deposited over the entire surface of the partially completed semiconductor, and the exposed surface of the photoresist is smoothed such as by heating at about 200.degree. C. The etched regions 3, 11 are surrounded by the resist 9; the silicide layer 3 will become part of the gate structure, while the insulating layer 11 will serve as a dummy gate, ultimately to be removed and replaced by a low resistance metal layer of the final gate structure.
As shown in FIG. 3(f), the photoresist film is then partly removed, as by reactive ion etching using oxygen as the gas etchant, until the upper surface of the insulating film 11 is exposed. In that condition, the device is then prepared for removal of the dummy gate 11 which is removed by wet etching which selectively attacks the silicon dioxide of the dummy gate, but will not substantially etch either the high melting point metal silicide layer 3 or the resist 9. At the conclusion of the wet etching step, the partially completed device takes the form illustrated in FIG. 3(g). Thereupon, a low resistance metal 10, preferably gold but alternatively aluminum, is deposited on the high melting point metal silicide film 3 (as well as on the photoresist 9) by evaporation, following which a lift-off process removes the photoresist with attached film leaving a self-aligned gold layer 10 deposited on the high melting point metal silicide gate 3.
In the MESFET thus produced, a low resistance metal layer such as gold or aluminum is self-aligned on the high melting point metal silicide gate, thereby to reduce the resistance of the gate electrode and increase the noise performance of the high efficiency field effect transistor, even at high frequencies.
However, the prior art production methods described above have certain deficiencies. Considering first the process illustrated in FIGS. 2(a)-2(d), it is found that deposition of the photoresist film 6 directly over the high melting point metal silicide layer 3 creates an uneven etching of the silicide layer. It is well known that high melting point metal silicides such as tungsten silicide are rather difficult to etch, and it is therefore found that depositing the resist directly over such difficult-to-etch layer will leave a constricted cross section as illustrated in FIG. 4(a). More particularly, the etching rate of the silicide layer 3 at a position close to the photoresist film 6 is slow, and the more rapid rate at lower levels where the photoresist film does not retard the etching process produces the constricted cross section shown in FIG. 4(a), making it difficult to achieve a highly precise fine pattern for the gate. When subsequent insulating films and metalized interconnections (which are formed in later process steps) are applied over such a poorly produced gate, cracks have a tendency to occur in the insulating film, potentially rendering the device defective. In greater detail, after the FET is formed, subsequent process steps (not shown in the figures) include the wiring or connecting of the formed microelectronic elements. An insulating film is first deposited over the surface of the semiconductor device, and a metal layer is then deposited over the insulator to form a wiring pattern. Excess metal is then removed using a patterning mask. The problem is illustrated in FIG. 4(b) which shows an insulating film 11(a) deposited on the constricted high melting point metal silicide film 3. It is seen that a crack C can occur in the insulating film 11(a) from the edge of the high melting point metal silicide film 3; when voltage is applied, crack C may cause the insulating film 11(a) to rupture.
With respect to the problems occasioned by utilization of the process illustrated in FIGS. 3(a)-3(h), other forms of abnormally etched elements can occur. More particularly, when the double film layer 3, 11 illustrated in FIG. 5(a) is processed by reactive ion etching, an abnormally etched portion A can occur at the interface of the high melting point metal silicide 3 and the insulating film 11 (see 5(b)). This abnormal etching appears to be caused by non-uniform stress distribution of the film, or by non-uniformity of the plasma due to an increase in oxygen concentration at the interface surface which results from the oxygen component of the silicon dioxide.
The problem is exacerbated when an acid wash is later used to remove residual products of the dry etching. The acid used for removing residuals can also etch certain of the deposited materials; the etching speed of the insulating film 11 at a portion close to the interface surface is high, and therefore, a further abnormality in the form of constricted portion B is formed as illustrated in FIG. 5(c). In later processing steps, when the photoresist film 9 is formed over the entire surface of the partially completed semiconductor, the photoresist fills the constricted portion B. When the dummy gate formed of the insulating film 11 is removed, and a low resistance metal layer 10 of gold or aluminum is deposited in its place, both side portions of the low resistance metal layer will be warped as shown in FIG. 3(h). When the circuit is further processed to include insulating films and metallized connecting layers (see FIG. 6(a)), the portions of the insulating film 12 which are located above the sharp edges of the low resistance metal layer 10 can be broken as shown at D in FIG. 6(b). This can cause short circuiting between the upper wiring layer 13 and the low resistance metal layer 10, thereby rendering the device defective.